Various design tools seek to simplify the tasks associated with designing an electronic system. For example, the System Generator high-level modeling system (HLMS) from Xilinx includes various tools that allow a user to assemble a design model using high-level functional blocks, simulate the design, and generate a realization of the design for a hardware platform such as a programmable logic device (PLD). The blocks used in creating the design may be selected from a library that is also part of the HLMS. An HLMS such as System Generator can substantially shorten the time required to develop a design by allowing a user to describe the system at an abstract level, while preserving functional behavior, and automatically generating the implementation. Traditional methodologies instead require specifying the functionality of the design in a hardware description language (HDL).
To fully support simulation and realization of a design, each block in an HLMS library typically consists of a component that is purely behavioral (bit- and cycle-accurate) that is used for simulation within the HLMS, and an equivalent component that can be automatically mapped into a realization (e.g., in a PLD) by conventional methods during code generation. Such methods include logic synthesis or direct mapping (a one-to-one mapping of logic components into resources in the target technology library). In the latter case, the implementation is referred to as structural. Although it is possible for a block in an HLMS to have a single component that supports both simulation and implementation, it is often the case that a separate simulation model is necessary because the implementation involves significant structural code that results in unacceptably slow simulation. By providing bit and cycle accurate behavior for the block, the HLMS enables the user to design at a high level of abstraction without losing control or visibility of the ultimate hardware realization.
It is desirable for an HLMS to include block libraries whose elements can be used to construct systems quickly. For example, an HLMS targeting digital signal processing (DSP) or digital communications applications could include blocks for finite impulse (FIR) and infinite impulse response (IIR) digital filters, fast Fourier transforms (FFTs), or error-correcting codecs. For high-level functions, there is often a significant amount of effort involved in creating an efficient implementation component. Providing a separate simulation model may provide a faster simulation model. However, constructing a separate bit and cycle accurate behavioral model for a complex IP block can be very time consuming.
For example, in the System Generator HLMS, a C++ simulation model may be created, including System Generator-specific data-types, classes, and interfaces, and used in simulating with the HLMS. Creating the C++ model for a complex IP block may require significant engineering resources.
The present invention may address one or more of the above issues.